The present invention relates to the connection of electrical components in integrated circuits.
In integrated circuits, or electronic chips, some electrical components like capacitors, resistors or any other passive or active element involved in the working of the circuit must be accurately calibrated. Such an accuracy cannot be achieved during the foundry process and these components are therefore precisely adjusted after the manufacture of the chips. FIG. 1 illustrates a conventional method of adjusting, for example, a capacitor. In parallel with a primary capacity Cm, low value adjusting capacities C1, C2, . . . Ci are provided, the whole forming an equivalent capacity equal to the sum of the capacities Cm, C1, C2, . . . Ci. Once the chip has been manufactured, the equivalent capacity is precisely adjusted by cutting, by means of a laser beam, one or several conducting lines p1, p2, . . . pi coupling the adjusting capacities to the primary capacity.
This method has the drawback that it is heavy to implement, and requires costly testing means and machines, as well as a significant amount of working time.
Another drawback of this method is that, for handling reasons, the cutting of the conducting lines is performed when the chips are still collectively present on the silicon mother plate, called "wafer". However, at this stage, some elements, which have sometimes to be taken into account for adjusting, are not yet connected to the chips. In particular, the electronic chip of a contactless chip card or of an electronic label supplied by electromagnetic induction comprises a circuit of the LC type (inductive-capacitive) whose resonance frequency must be tuned to the oscillating frequency of an inducting magnetic field which enables the working of the chip. As the coil L of the LC circuit is generally soldered to the chip during the last manufacturing stage, adjusting the capacity C on the wafer does not allow to compensate the manufacture tolerances of the coil L and to obtain the accurate value LC. Furthermore, various stray capacities appearing when the chip is supplied are not taken into account.
In the prior art, the Japanese Abstract JP6084384 describes a clock circuit whose time base is determined by capacities in parallel able to be commutated by switches controlled by non-volatile memory cells. Also, the U.S. Pat. No. 4,814,640 describes a programmable component comprising a plurality of parallel components commutated by switches controlled by programmable memory cells.
An idea of the present invention is to provide a programmable capacity in the LC resonant circuit of a contactless electronic chip, so as to tune the LC circuit by programming the capacity at the moment when the chip is put into service.